The invention relates to a semiconductor integrated circuit device having a plurality of insulated gate field effect transistors (hereinafter abbreviated as "IGFET's"), more particularly to such a device operable at a high speed and having a high reliability.
The degree of integration of integrated circuit devices having IGFET's has been increasing at a growing rate due to the use of the polycrystalline silicon gate technique and owing to the progress of the technique of micro-fine patterning. The realization of the high degree of integration made possible by the micro-fine patterning of the silicon wiring has brought about a great enhancement of the operating speed of integrated circuits, but has also resulted in a significant delay in signal transmission time due to the resistance of the polycrystalline silicon wiring.
As one solution for this problem, attempts have been made by many investigators to replace all the thin film pattern of polycrystalline silicon used for gate electrodes and wirings by thin film patterns of low-resistance high-melting-point metal, or refractory metal, such as molybdenum, tungsten, etc. However, the replacement of the gate electrode along with the same level wiring which is continuous to the gate electrode (for the sake of simplicity, hereinafter generally called "gate wiring", which is used in the form of "polycrystalline silicon gate wiring", "high-melting-point metal gate wiring", etc.) and is made of polycrystalline silicon, by a high-melting-point metal gate wiring made of molybdenum or the like still involves a number of problems, and therefore no single method for replacement has yet been established. The problem relating to "direct contact" which will be defined later is one of the important problems among these methods.
A circuit construction shown in FIG. 1, that is, an inverter circuit of the so-called E/D construction is one of the most important basic constructions among the IGFET type integrated circuits. In this circuit, a transistor Q.sub.1 is an enhancement type (E-type) driving IGFET, and the other transistor Q.sub.2 is a depletion typw (D-type) load IFGET. If this inverter is conventionally formed by a silicon gate IGFET, for instance, it can be formed in the pattern arrangement as shown in FIGS. 2A and 2B. In FIG. 2B, dotted regions represent polycrystalline silicon gate wirings. In these figures, reference numeral 1 designates a junction point 1 in FIG. 1, numeral 2 a p-type silicon substrate, numeral 3 a field oxide film, numerals 4 and 4' gate oxide films, numerals 5 and 5' doped polycrystalline silicon gate wirings, numerals 6, 6' and 6" n.sup.+ source, drain regions, numeral 7 a phosphorus glass film, and numerals 8 aluminum wiring layers. In this silicon gate structure, as will be seen from FIGS. 2A and 2B, the polycrystalline silicon gate electrode 5 of the load transistor Q.sub.2 is in itself used as a wiring for connecting to the n.sup.+ region 6 of the substrate, and thus the junction point or the contact section 1 in FIG. 1 is realized by directly connecting the extension of the gate electrode 5 onto the surface of the semiconductor substrate without the intermediary of a metallic wiring. Throughout this specification, the term "direct contact" shall mean such direct connections between the extension of the polycrystalline silicon layer and the surface of the semiconductor substrate. Where the "direct contact" is employed, freedom in pattern arrangement becomes large and the area necessitated for the pattern arrangement can be made small. Therefore, it is a common technique used in silicon gate structures.
Now, if the polycrystalline silicon gate wiring in the silicon gate structure should be in itself replaced by a high-melting-point metal gate wiring as of molybdenum or the like, then the direct contact 1 in FIGS. 2A and 2B would be a contact between monocrystalline silicon (substrate) and a high-melting-point metal. However, the presently known direct contact technique between monocrystalline silicon and a high-melting-point metal cannot be used in such a case for the following reasons. That is, in the manufacturing process of an IGFET type integrated circuit, the highly-doped source and drain regions 6' 6" and 6 of the IGFETs are formed by ion implantation and thermal diffusion after formation of the gate electrode pattern and thus after formation of the direct contact. Therefore, it is necessary that a heat treatment process at about 1000.degree. C. be applied after formation of the contact. With a high-melting-point metal gate structure of molybdenum, if a high-temperature heat treatment process at about 1000.degree. C. is applied to the contact between the high-melting-point metal and the substrate monocrystalline silicon, then silicide of the high-melting-point metal is formed by the reaction between the high-melting-point metal and the substrate monocrystalline silicon, resulting in volume reduction and the generation of a significant stress in the contact section. Also, in some cases, the reaction for formation of silicide does not proceed uniformly, and an undesirable unevenness arises on the surface of the reaction layer. Such stress and surface unevenness would sometimes induce crystal defects in the substrate silicon at the contact section, would cause deterioration of electric properties at the contact section and at the p-n junction existing near the contact, and may even result in peeling-off of the silicide layer from the substrate silicon. For these reasons, the mere replacement of the polycrystalline silicon pattern in the heretofore known silicon gate structure a high-melting-point metal pattern is not acceptable in the manufacturing of IGFET type integrated circuits.
Accordingly, when a high-melting-point gate structure is employed, the connection between the gate electrode of the load transistor Q.sub.2 and the contact section 1 is formed at the same time as the metal wiring in the top layer (normally, aluminum aluminum alloy wiring), without employing the direct contact. One example of such a structure is shown in FIGS. 3A and 3B. FIG. 3B is a cross-sectional view taken along line B--B' in FIG. 3A as viewed in the direction of the arrows. In these figures, a connecting wiring layer 12' between the high-melting-point metal gate 10 of load transistor Q.sub.2 and a high concentration doping region 11 is formed at the same time as aluminum wirings 12 such as a ground line GND, a power supply V.sub.DD, etc. are formed, and on the same level as these internal wirings 12. The connecting wiring layer 12' such as an aluminum layer is connected to the region 11 at the contact section 9. In the illustrated example, this connecting wiring layer 12' is formed with a structure similar to that of a direct contact so that no increase of contact area may arise as compared to the case of a direct contact. In other words, the layer 12' is formed in a single contact hole. If desired, contact holes 14 and 15 can be provided respectively on the gate electrode and on the high concentration region 11, and the connecting wiring layer 12" can bridge between these holes as shown in FIG. 4, but in such a case there is a disadvantage in that increase in the area for pattern arrangement is generally inevitable. Moreover, the prior art structure shown in FIGS. 3A and 3B having a single contact hole cannot be used practically for the following reasons. In the case of forming a single contact hole as shown in FIG. 3, after an insulating film 13 has been formed it is necessary to open the contact hole by etching as seen in FIG. 3B, and the etching time is determined to be rather long so that, due to fluctuations of the etching speed within a wafer due to unevenness of the surface condition and thickness of the insulating film 13 and the gate oxide film as well as the concentration of an effective etching component in the etching liquid, etching at a fixed rate will normally result in over-etching. Then, in the case of the united contact section 9, the gate electrode 10 is made of a material that cannot be etched normally in the etching process for opening the contact hole, and hence the over-etching will result in etching of the gate oxide film 4 under the gate electrode 10, resulting in an undercut. In the case where the undercut has been formed, if the reentrance of the aluminum connecting layer 12' into the undercut is poor, a hollow space 16 will remain as shown in FIG. 5A, or even if the reentrance is well effected, there will occur the situation where the aluminum connecting layer 12' makes direct contact or short contact with the channel region at the part 16' as shown in FIG. 5B, since, due to the increasing density of integrated circuits, manufacturing processes are employed which result in little lateral diffusion of dopant. Accordingly, in the case of employing the united contact having the structure as shown in FIG. 3, more accurate control for the manufacturing process is required than in the case of the prior art silicon gate structure.
Furthermore, in the case of employing the united contact having the structure as shown in FIG. 3, since the aluminum connecting layer 12' at the single contact hole and the other aluminum wiring 12 for internal connection are formed at the same level, a restriction is imposed upon the pattern arrangement that the aluminum internal wirings 12 must be arranged so as to avoid the single contact hole or to avoid the aluminum connecting layer 12'. In a large scale integrated circuit, inverters having the circuit construction as shown in FIG. 1 are disposed in a very great number at a high density and the density of the aluminum wirings 12 for connecting them is also necessarily high. Therefore, the requirement that the aluminum internal wirings 12 must be arranged so as to avoid the single contact holes, is a great.